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semiconductor technical data 1 rev 4 ? motorola, inc. 1997 2/97 the MPC950/951 are 3.3v compatible, pll based clock driver devices targeted for high performance clock tree designs. with output frequencies of up to 180mhz and output skews of 375ps the MPC950 is ideal for the most demanding clock tree designs. the devices employ a fully differential pll design to minimize cycletocycle and long term jitter. this parameter is of significant importance when the clock driver is providing the reference clock for pll's on board today's microprocessors and asic's. the devices offer 9 low skew outputs, the outputs are configurable to support the clocking needs of the various high performance microprocessors. ? fully integrated pll ? oscillator or crystal reference input ? output frequency up to 180mhz ? outputs disable in high impedance ? compatible with powerpc ? , intel and high performance risc microprocessors ? tqfp packaging ? output frequency configurable ? 100ps typical cycletocycle jitter two selectable feedback division ratios are available on the MPC950 to provide input reference clock flexibility. the fbsel pin will choose between a divide by 8 or a divide by 16 of the vco frequency to be compared with the input reference to the MPC950. the internal vco is running at either 2x or 4x the high speed output, depending on configuration, so that the input reference will be either one half, one fourth or one eighth the high speed output. the mpc951 replaces the crystal oscillator and internal feedback of the MPC950 with a differential pecl reference input and an external feedback input. these features allow for the mpc951 to be used as a zero delay, low skew fanout buffer. in addition, the external feedback allows for a wider variety of inputtooutput frequency relationships. the mpc951 ref_sel pin allows for the selection of an alternate lvcmos input clock to be used as a test clock or to provide the reference for the pll from an lvcmos source. the MPC950 provides an external test clock input for scan clock distribution or system diagnostics. in addition the ref_sel pin allows the user to select between a crystal input to an onboard oscillator for the reference or to chose a ttl level oscillator input directly. the onboard crystal oscillator requires no external components beyond a series resonant crystal. both the MPC950 and mpc951 are fully 3.3v compatible and require no external loop filter components. all inputs accept lvcmos or lvttl compatible levels while the outputs provide lvcmos levels with the capability to drive terminated 50 w transmission lines. select inputs do not have internal pullup/pulldown resistors and thus must be set externally. if the pecl_clk inputs are not used, they can be left open. for series terminated 50 w lines, each of the MPC950/951 outputs can drive two traces giving the device an effective fanout of 1:18. the device is packaged in a 7x7mm 32lead tqfp package to provide the optimum combination of board density and performance. powerpc is a trademark of international business machines corporation. pentium is a trademark of intel corporation.

low voltage pll clock driver fa suffix 32lead tqfp package case 873a02
MPC950 mpc951 motorola timing solutions br1333 e rev 6 2 MPC950 logic diagram 2/ 4 qa vco 200480mhz phase detector lpf 8/ 16 mr/oe xtal osc fselc fselb fbsel xtal2 xtal1 tclk 4/ 8 qb 4/ 8 qc0 4/ 8 qd0 qc1 qd1 qd2 qd3 qd4 fseld ref_sel pll_en fsela poweron reset (pull down) mr/oe gndo qb vcco qa gndo tclk pll_en ref_sel qd2 vcco qd3 gndo qd4 vcco xtal2 qc0 vcco qc1 gndo qd0 vcco qd1 gndo vcca fbsel fsela fselb fselc fseld gndi xtal1 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 MPC950 function tables ref_sel function 1 0 tclk xtal_osc pll_en function 1 0 pll enabled pll bypass fbsel function 1 0 8 16 mr/oe function 1 0 outputs disabled outputs enabled fseln function 1 0 qa = 4; qb:d = 8 qa = 2; qb:d = 4
MPC950 mpc951 timing solutions br1333 e rev 6 3 motorola mpc951 logic diagram 2/ 4 qa vco 200550mhz phase detector lpf mr/oe fselc fselb pecl_clk pecl_clk tclk 4/ 8 qb 4/ 8 qc0 4/ 8 qd0 qc1 qd1 qd2 qd3 qd4 fseld ref_sel pll_en fsela poweron reset ext_fb (pull up) (pull down) mr/oe pecl_clk gndo qb vcco qa gndo tclk pll_en ref_sel qd2 vcco qd3 gndo qd4 vcco qc0 vcco qc1 gndo qd0 vcco qd1 gndo vcca ext_fb fsela fselb fselc fseld gndi pecl_clk 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 mpc951 function tables ref_sel function 1 0 tclk pecl_clk pll_en function 1 0 pll enabled pll bypass mr/oe function 1 0 outputs disabled outputs enabled fseln function 1 0 qa = 4; qb:d = 8 qa = 2; qb:d = 4
MPC950 mpc951 motorola timing solutions br1333 e rev 6 4 function table MPC950/951 inputs outputs totals fsela fselb fselc fseld qa(1) qb(1) qc(2) qd(5) total 2x total x total x/2 0 0 0 0 2x x x x 1 8 0 0 0 0 1 2x x x x/2 1 3 5 0 0 1 0 2x x x/2 x 1 6 2 0 0 1 1 2x x x/2 x/2 1 1 7 0 1 0 0 2x x/2 x x 1 7 1 0 1 0 1 2x x/2 x x/2 1 2 6 0 1 1 0 2x x/2 x/2 x 1 3 5 0 1 1 1 2x x/2 x/2 x/2 1 0 8 1 0 0 0 x x x x 0 9 0 1 0 0 1 x x x x/2 0 4 5 1 0 1 0 x x x/2 x 0 7 2 1 0 1 1 x x x/2 x/2 0 2 7 1 1 0 0 x x/2 x x 0 8 1 1 1 0 1 x x/2 x x/2 0 3 6 1 1 1 0 x x/2 x/2 x 0 6 3 1 1 1 1 x x/2 x/2 x/2 0 1 8 note: x = f vco /4; 200mhz < f vco < 480mhz. absolute maximum ratings* symbol parameter min max unit v cc supply voltage 0.3 4.6 v v i input voltage 0.3 v dd + 0.3 v i in input current 20 ma t stor storage temperature range 40 125 c * absolute maximum continuous ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation under absolutemaximumrated conditions is not implied. dc characteristics (t a = 0 to 70 c, v cc = 3.3v 5%) symbol characteristic min typ max unit condition v ih input high voltage lvcmos inputs 2.0 3.6 v v il input low voltage lvcmos inputs 0.8 v v pp peaktopeak input voltage pecl_clk 300 1000 mv v cmr common mode range pecl_clk v cc 2.0 v cc 0.6 mv note 1. v oh output high voltage 2.4 v i oh = 40ma, note 2. v ol output low voltage 0.5 v i ol = 40ma, note 2. i in input current 120 m a c in input capacitance 4 pf c pd power dissipation capacitance 25 pf per output i cc maximum quiescent supply current 90 115 ma all vcc pins i ccpll maximum pll supply current 15 20 ma vcca pin only 1. v cmr is the difference from the most positive side of the differential input signal. normal operation is obtained when the ahigho input is within the v cmr range and the input swing lies within the v pp specification. 2. the MPC950/951 outputs can drive series or parallel terminated 50 w (or 50 w to v cc /2) transmission lines on the incident edge (see applications info section).
MPC950 mpc951 timing solutions br1333 e rev 6 5 motorola pll input reference characteristics (t a = 0 to 70 c) symbol characteristic min max unit condition t r , t f tclk input rise/falls 3.0 ns f ref reference input frequency note 1. note 1. mhz f xtal crystal oscillator frequency 10 25 mhz note 2. f refdc reference input duty cycle 25 75 % 1. maximum and minimum input reference is limited by the vco lock range and the feedback divider for the tclk or pecl_clk inputs. 2. see applications info section for more crystal information. ac characteristics (t a = 0 c to 70 c, v cc = 3.3v 5% ) symbol characteristic min typ max unit condition t r , t f output rise/fall time 0.10 1.0 ns 0.8 to 2.0v t pw output duty cycle t cycle /21000 t cycle /2+1000 ps t sk(o) outputtooutput skews same frequencies 200 375 ps different frequencies qa fmax < 150mhz qa fmax > 150mhz 325 500 750 f vco pll vco feedback = vco/4 lock feedback = vco/8 range feedback = vco/16 200 200 200 480 480 480 mhz mpc951 MPC950 or 951 MPC950 f max maximum output qa ( 2) frequency qa/qb ( 4) qb ( 8) 180 120 60 mhz t pd input to ext_fb delay tclk (note 1.) pecl_clk 50 950 250 770 400 600 ps f ref = 50mhz feedback=vco/8 t plz , hz output disable time 7 ns t pzl output enable time 6 ns t jitter cycletocycle jitter (peaktopeak) 100 ps note 2. t lock maximum pll lock time 10 ms 1. the specification is guaranteed for the mpc951 only. the t pd window is specified for a 50mhz input reference clock. the window will enlarge/reduce proportionally from the minimum limits with an increase/decrease of the input reference clock period. 2. see applications info section for more jitter information. applications information programming the MPC950/951 the MPC950/951 clock driver outputs can be configured into several frequency relationships, in addition the external feedback option of the mpc951 allows for a great deal of flexibility in establishing unique input to output frequency relationships. the output dividers for the four output groups allows the user to configure the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. the use of even dividers ensures that the output duty cycle is always 50%. table 1 illustrates the various output configurations, the table describes the outputs using the vco frequency as a reference. as an example for a 4:2:1 relationship the qa outputs would be set at vco/2, the qb's and qc's at vco/4 and the qd's at vco/8. these settings will provide output frequencies with a 4:2:1 relationship. the division settings establish the output relationship, but one must still ensure that the vco will be stable given the frequency of the outputs desired. the feedback frequency should be used to situate the vco into a frequency range in which the pll will be stable. the design of the pll is such that for output frequencies between 25 and 180mhz the MPC950/951 can generally be configured into a stable region. the relationship between the input reference and the output frequency is also very flexible. table 2 shows the multiplication factors between the inputs and outputs for the MPC950. for external feedback (mpc951) table 1 can be used to determine the multiplication factor, there are too many potential combinations to tabularize the external feedback condition. figure 1 through figure 6 illustrates several programming possibilities, although not exhaustive it is representative of the potential applications.
MPC950 mpc951 motorola timing solutions br1333 e rev 6 6 using the mpc951 as a zero delay buffer the external feedback option of the mpc951 clock driver allows for its use as a zero delay buffer. by using one of the outputs as a feedback to the pll the propagation delay through the device is eliminated. the pll works to align the output edge with the input reference edge thus producing a near zero delay. the input reference frequency affects the static phase offset of the pll and thus the relative delay between the inputs and outputs. when used as a zero delay buffer the mpc951 will likely be in a nested clock tree application. for these applications the mpc951 offers a lvpecl clock input as a pll reference. this allows the user to use lvpecl as the primary clock distribution device to take advantage of its far superior skew performance. the mpc951 then can lock onto the lvpecl reference and translate with near zero delay to low skew lvcmos outputs. clock trees implemented in this fashion will show significantly tighter skews than trees developed from cmos fanout buffers. to minimize parttopart skew the external feedback option again should be used. the pll in the mpc951 decouples the delay of the device from the propagation delay variations of the internal gates. from the specification table one sees a tpd variation of only 200ps, thus for multiple devices under identical configurations the parttopart skew will be around 1000ps (350ps for tpd variation plus 350ps outputtooutput skew plus 300ps for i/o jitter). by running the devices at the highest possible input reference, this partto part skew can be minimized. higher input reference frequencies will minimize both i/o jitter and t pd variations. table 1. programmable output frequency relationships inputs outputs fsela fselb fselc fseld qa qb qc qd 0 0 0 0 vco/2 vco/4 vco/4 vco/4 0 0 0 1 vco/2 vco/4 vco/4 vco/8 0 0 1 0 vco/2 vco/4 vco/8 vco/4 0 0 1 1 vco/2 vco/4 vco/8 vco/8 0 1 0 0 vco/2 vco/8 vco/4 vco/4 0 1 0 1 vco/2 vco/8 vco/4 vco/8 0 1 1 0 vco/2 vco/8 vco/8 vco/4 0 1 1 1 vco/2 vco/8 vco/8 vco/8 1 0 0 0 vco/4 vco/4 vco/4 vco/4 1 0 0 1 vco/4 vco/4 vco/4 vco/8 1 0 1 0 vco/4 vco/4 vco/8 vco/4 1 0 1 1 vco/4 vco/4 vco/8 vco/8 1 1 0 0 vco/4 vco/8 vco/4 vco/4 1 1 0 1 vco/4 vco/8 vco/4 vco/8 1 1 1 0 vco/4 vco/8 vco/8 vco/4 1 1 1 1 vco/4 vco/8 vco/8 vco/8 table 2. input reference versus output frequency relationships (MPC950 only) fb_sel = `1' fb_sel = `0' config fsela fselb fselc fseld qa qb qc qd qa qb qc qd 1 0 0 0 0 4x 2x 2x 2x 8x 4x 4x 4x 2 0 0 0 1 4x 2x 2x x 8x 4x 4x 2x 3 0 0 1 0 4x 2x x 2x 8x 4x 2x 4x 4 0 0 1 1 4x 2x x x 8x 4x 2x 2x 5 0 1 0 0 4x x 2x 2x 8x 2x 4x 4x 6 0 1 0 1 4x x 2x x 8x 2x 4x 2x 7 0 1 1 0 4x x x 2x 8x 2x 2x 4x 8 0 1 1 1 4x x x x 8x 2x 2x 2x 9 1 0 0 0 2x 2x 2x 2x 4x 4x 4x 4x 10 1 0 0 1 2x 2x 2x x 4x 4x 4x 2x 11 1 0 1 0 2x 2x x 2x 4x 4x 2x 4x 12 1 0 1 1 2x 2x x x 4x 4x 2x 2x 13 1 1 0 0 2x x 2x 2x 4x 2x 4x 4x 14 1 1 0 1 2x x 2x x 4x 2x 4x 2x 15 1 1 1 0 2x x x 2x 4x 2x 2x 4x 16 1 1 1 1 2x x x x 4x 2x 2x 2x
MPC950 mpc951 timing solutions br1333 e rev 6 7 motorola MPC950 figure 1. dual frequency configuration fsela `1' fselb `1' fselc `1' fseld `0' input ref 16.66mhz 66.66mhz qa 33.33mhz qb 33.33mhz qc 1 1 2 MPC950 figure 2. dual frequency configuration `1' `0' `0' `1' input ref 33.33mhz 66.66mhz qa 66.66mhz qb 66.66mhz qc 1 1 2 fbsel `0' fbsel `1' fsela fselb fselc fseld 66.66mhz qd 5 33.33mhz qd 5 MPC950 figure 3. dual frequency configuration fsela `1' fselb `1' fselc `1' fseld `1' input ref 16.66mhz 66.66mhz qa 33.33mhz qb 33.33mhz qc 1 1 2 MPC950 figure 4. triple frequency configuration `0' `0' `1' `1' input ref 20mhz 160mhz qa 80mhz qb 40mhz qc 1 1 2 fbsel `0' fbsel `0' fsela fselb fselc fseld 33.33mhz qd 5 40mhz qd 5 mpc951 `1' `0' `0' `0' input ref 75mhz ext_fb 1 mpc951 `0' `0' `0' `1' input ref 25mhz ext_fb 1 fsela fselb fselc fseld fsela fselb fselc fseld 75mhz qa 75mhz qb 75mhz qc 1 1 2 75mhz qd 5 figure 5. azeroo delay buffer figure 6. azeroo delay frequency multiplier 1 100mhz qa 50mhz qb 50mhz qc 1 1 2 25mhz qd 5 jitter performance of the MPC950/951 with the clock rates of today's digital systems continuing to increase more emphasis is being placed on clock distribution design and management. among the issues being addressed is system clock jitter and how that affects the overall system timing budget. the MPC950/951 was designed to minimize clock jitter by employing a differential bipolar pll as well as incorporating numerous power and ground pins in the design. the following few paragraphs will outline the jitter performance of the MPC950/951, illustrate the measurement limitations and provide guidelines to minimize the jitter of the device. the most commonly specified jitter parameter is cycletocycle jitter. unfortunately with today's high performance measurement equipment there is no way to measure this parameter for jitter performance in the class demonstrated by the MPC950/951. as a result different methods are used which approximate cycletocycle jitter. the typical method of measuring the jitter is to accumulate a large number of cycles, create a histogram of the edge placements and record peaktopeak as well as standard deviations of the jitter. care must be taken that the measured edge is the edge immediately following the trigger edge. if this is not the case the measurement inaccuracy will add significantly to the measured jitter. the oscilloscope cannot collect adjacent pulses, rather it collects data from a very large sample of pulses. it is safe to assume that collecting pulse information in this mode will produce jitter values somewhat larger than if consecutive cycles were measured, therefore, this measurement will represent an upper bound of cycletocycle jitter. most likely, this is a conservative estimate of the cycletocycle jitter. there are two sources of jitter in a pll based clock driver, the commonly known random jitter of the pll and the less intuitive jitter caused by synchronous, different frequency outputs switching. for the case where all of the outputs are
MPC950 mpc951 motorola timing solutions br1333 e rev 6 8 switching at the same frequency the total jitter is exactly equal to the pll jitter. in a device, like the MPC950/951, where a number of the outputs can be switching synchronously but at different frequencies a amultimodalo jitter distribution can be seen on the highest frequency outputs. because the output being monitored is affected by the activity on the other outputs it is important to consider what is happening on those other outputs. from figure 9, one can see for each rising edge on the higher frequency signal the activity on the lower frequency signal is not constant. the activity on the other outputs tends to alter the internal thresholds of the device such that the placement of the edge being monitored is displaced in time. because the signals are synchronous the relationship is periodic and the resulting jitter is a compilation of the pll jitter superimposed on the displaced edges. when histograms are plotted the jitter looks like a amultimodalo distribution as pictured in figure 9. depending on the size of the pll jitter and the relative displacement of the edges the amultimodalo distribution will appear truly amultimodalo or simply like a afato gaussian distribution. again note that in the case where all the outputs are switching at the same frequency there is no edge displacement and the jitter is reduced to that of the pll. figure 7. pll jitter and edge displacement 1212 12 1232 12 123 3 peaktopeak pll jitter peaktopeak period jitter peaktopeak pll jitter peaktopeak period jitter figure 10 graphically represents the pll jitter of the MPC950/951. the data was taken for several different output configurations. by triggering on the lowest frequency output the pll jitter can be measured for configurations in which outputs are switching at different frequencies. as one can see in the figure the pll jitter is much less dependent on output configuration than on internal vco frequency. figure 8. rms pll jitter versus vco frequency 0 5 10 15 20 25 30 35 40 160 240 320 400 480 560 conf 1 conf 2 conf 3 conf 1 = all outputs at the same frequency conf 2 = 4 outputs at x, 5 outputs at x/2 conf 3 = 1 output at x, 8 outputs at x/4 vco frequency (mhz) rms jitter (ps) figure 9. peaktopeak period jitter versus vco frequency 150 200 250 300 350 400 160 240 320 400 480 560 conf 2 conf 3 conf 2 = 4 outputs at x, 5 outputs at x/2 conf 3 = 1 output at x, 8 outputs at x/4 vco frequency (mhz) paektopeak jitter (ps) two different configurations were chosen to look at the period displacement caused by the switching outputs. configuration 3 is considered worst case as the atrimodalo distribution (as pictured in figure 9) represents the largest spread between distribution peaks. configuration 2 is considered a typical configuration with half the outputs at a high frequency and the remaining outputs at one half the high frequency. for these cases the peaktopeak numbers are reported in figure 11 as the sigma numbers are useless because the distributions are not gaussian. for situations where the outputs are synchronous and switching at different frequencies the measurement technique described here is insufficient to use for establishing guaranteed limits. other techniques are currently being investigated to identify a more accurate and repeatable measurement so that guaranteed
MPC950 mpc951 timing solutions br1333 e rev 6 9 motorola limits can be provided. the data generated does give a good indication of the general performance, a performance that in most cases is well within the requirements of today's microprocessors. finally from the data there are some general guidelines that, if followed, will minimize the output jitter of the device. first and foremost always configure the device such that the vco runs as fast as possible. this is by far the most critical parameter in minimizing jitter. second keep the reference frequency as high as possible. more frequent updates at the phase detector will help to reduce jitter. note that if there is a tradeoff between higher reference frequencies and higher vco frequency always chose the higher vco frequency to minimize jitter. the third guideline may be the most difficult, and in some cases impossible, to follow. try to minimize the number of different frequencies sourced from a single chip. the fixed edge displacement associated with the switching noise in most cases nearly doubles the aeffectiveo jitter of a high speed output. power supply filtering the MPC950/951 is a mixed analog/digital product and as such it exhibits some sensitivities that would not necessarily be seen on a fully digital product. analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. the MPC950/951 provides separate power supplies for the output buffers (vcco) and the phaselocked loop (vcca) of the device. the purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phaselocked loop. in a controlled environment such as an evaluation board this level of isolation is sufficient. however, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. the simplest form of isolation is a power supply filter on the vcca pin for the MPC950/951. figure 10 illustrates a typical power supply filter scheme. the MPC950/951 is most susceptible to noise with spectral content in the 1khz to 1mhz range. therefore the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop that will be seen between the v cc supply and the vcca pin of the MPC950/951. from the data sheet the i vcca current (the current sourced through the vcca pin) is typically 15ma (20ma maximum), assuming that a minimum of 3.0v must be maintained on the vcca pin very little dc voltage drop can be tolerated when a 3.3v v cc supply is used. the resistor shown in figure 10 must have a resistance of 1015 w to meet the voltage drop criteria. the rc filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20khz. as the noise frequency crosses the series resonant point of an individual capacitor it's overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. it is recommended that the user start with an 810 w resistor to avoid potential v cc drop problems and only move to the higher value resistors when a higher level of attenuation is shown to be needed. figure 10. power supply filter pll_vcc vcc MPC950/951 0.01 m f 22 m f 0.01 m f 3.3v r s =515 w although the MPC950/951 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential pll) there still may be applications in which overall performance is being degraded due to system power supply noise. the power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. using the onboard crystal oscillator the MPC950/951 features an onboard crystal oscillator to allow for seed clock generation as well as final distribution. the onboard oscillator is completely self contained so that the only external component required is the crystal. as the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC950/951 as possible to avoid any board level parasitics. to facilitate colocation surface mount crystals are recommended, but not required.
MPC950 mpc951 motorola timing solutions br1333 e rev 6 10 the oscillator circuit is a series resonant circuit as opposed to the more common parallel resonant circuit, this eliminates the need for large onboard capacitors. because the design is a series resonant design for the optimum frequency accuracy a series resonant crystal should be used (see specification table below). unfortunately most off the shelf crystals are characterized in a parallel resonant mode. however a parallel resonant crystal is physically no different than a series resonant crystal, a parallel resonant crystal is simply a crystal which has been characterized in its parallel resonant mode. therefore in the majority of cases a parallel specified crystal can be used with the MPC950/951 with just a minor frequency error due to the actual series resonant frequency of the parallel resonant specified crystal. typically a parallel specified crystal used in a series resonant mode will exhibit an oscillatory frequency a few hundred ppm lower than the specified value. for most processor implementations a few hundred ppm translates into khz inaccuracies, a level which does not represent a major issue. table 3. crystal specifications parameter value crystal cut fundamental at cut resonance series resonance* frequency tolerance 75ppm at 25 c frequency/temperature stability 150ppm 0 to 70 c operating range 0 to 70 c shunt capacitance 57pf equivalent series resistance (esr) 50 to 80 w max correlation drive level 100 m w aging 5ppm/yr (first 3 years) * see accompanying text for series versus parallel resonant discussion. the MPC950/951 is a clock driver which was designed to generate outputs with programmable frequency relationships and not a synthesizer with a fixed input frequency. as a result the crystal input frequency is a function of the desired output frequency. for a design which utilizes the external feedback to the pll the selection of the crystal frequency is straight forward; simply chose a crystal which is equal in frequency to the fed back signal. to determine the crystal required to produce the desired output frequency for an application which utilizes internal feedback the block diagram of figure 11 should be used. the p and the m values for the MPC950/951 are also included in figure 11. the m values can be found in the configuration tables included in this applications section. figure 11. pll block diagram f ref phase detector qn vco lpf p n m f ref fqn n p m f ref f vco m ,f vco fqnnp m = 8 (fbsel = `1'), 16(fbsel = `0') p = 1 for the MPC950/951 clock driver, the following will provide an example of how to determine the crystal frequency required for a given design. given: qa = 160mhz qb = 80mhz qc = 40mhz qd = 40mhz fbsel = `0' f ref fqn n p m from table 3 fqd = vco/8 then n = 8 or fqa = vco/2 then n = 2 from figure 11 m = 16 and p = 1 f ref 4081 16 20mhz or 16021 16 20mhz driving transmission lines the MPC950/951 clock driver was designed to drive high speed signals in a terminated transmission line environment. to provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. with an output impedance of less than 10 w the drivers can drive either parallel or series terminated transmission lines. for more information on transmission lines the reader is referred to application note an1091 in the timing solutions brochure (br1333/d). in most high performance clock networks pointtopoint distribution of signals is the method of choice. in a pointtopoint scheme either series terminated or parallel terminated transmission lines can be used. the parallel technique terminates the signal at the end of the line with a 50 w resistance to vcc/2. this technique draws a fairly high level of dc current and thus only a single terminated line can
MPC950 mpc951 timing solutions br1333 e rev 6 11 motorola be driven by each output of the MPC950/951 clock driver. for the series terminated case however there is no dc current draw, thus the outputs can drive multiple series terminated lines. figure 12 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. when taken to its extreme the fanout of the MPC950/951 clock driver is effectively doubled due to its capability to drive multiple lines. figure 12. single versus dual transmission lines 7 w in MPC950/951 output buffer r s = 43 w z o = 50 w outa 7 w in MPC950/951 output buffer r s = 43 w z o = 50 w outb0 r s = 43 w z o = 50 w outb1 the waveform plots of figure 13 show the simulation results of an output driving a single line vs two lines. in both cases the drive capability of the MPC950/951 output buffers is more than sufficient to drive 50 w transmission lines on the incident edge. note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. this suggests that the dual line driving need not be used exclusively to maintain the tight outputtooutput skew of the MPC950/951. the output waveform in figure 13 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. the parallel combination of the 43 w series resistor plus the output impedance does not match the parallel combination of the line impedances. the voltage wave launched down the two lines will equal: vl = vs ( zo / (rs + ro +zo)) zo = 50 w || 50 w rs = 43 w || 43 w ro = 7 w vl = 3.0 (25 / (21.5 + 7 + 25) = 3.0 (25 / 53.5) = 1.40v at the load end the voltage will double, due to the near unity reflection coefficient, to 2.8v. it will then increment towards the quiescent 3.0v in steps separated by one round trip delay (in this case 4.0ns). figure 13. single versus dual waveforms time (ns) voltage (v) 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 8 10 12 14 outb t d = 3.9386 outa t d = 3.8956 in since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. to better match the impedances when driving multiple lines the situation in figure 14 should be used. in this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. figure 14. optimized dual line termination 7 w MPC950/951 output buffer r s = 36 w z o = 50 w r s = 36 w z o = 50 w 7 w + 36 w 36 w = 50 w 50 w 25 w = 25 w spice level output buffer models are available for engineers who want to simulate their specific interconnect schemes. in addition iv characteristics are in the process of being generated to support the other board level simulators in general use.
MPC950 mpc951 motorola timing solutions br1333 e rev 6 12 outline dimensions fa suffix tqfp package case 873a02 issue a detail y a s1 v b 1 8 9 17 25 32 ae ae p detail y base n j d f metal section aeae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ab is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums t, u, and z to be determined at datum plane ab. 5. dimensions s and v to be determined at seating plane ac. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ab. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc detail ad a1 b1 v1 4x s 4x b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref 9 t z u tu 0.20 (0.008) z ac tu 0.20 (0.008) z ab 0.10 (0.004) ac ac ab m 8x t, u, z tu m 0.20 (0.008) z ac
MPC950 mpc951 timing solutions br1333 e rev 6 13 motorola motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 5405; denver, colorado 80217. 3036752140 or 18004412447 3142 tatsumi kotoku, tokyo 135, japan. 81335218315 mfax ? : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://www.mot.com/sps/ 51 ting kok r oad, tai po, n.t., hong kong. 85226629298 MPC950/d ?

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